1. Project ( They are expecting the project to be done on FPGA minimum ).
2. Design a circuit that decides whether an input infinite serial stream of bits is divisible by 5 or not. ( For eg. 10 is not div but with the next bit 101 is div and so on). Atleast explain it in the form of a state diagram.
3. What is the maximum frequency of your project? Can't you still increase it? How/Why? ( Yes/No )
4. What are setup and hold times?
5. How many clocks did your project use? How did you handle them?
6. What are the default values of reg and wire data types?
7. What is the difference between blocking and non blocking assignment? ( Both conceptual and
hardware based ).
8. How do you decide whether to use Synchronous and Asynchronous resets?
- Questions asked mostly on project ( In depth )
- No questions asked on tools.
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